1. Field of the Invention
The present invention relates to a plasma processing apparatus or a plasma processing method that processes a substrate-like sample such as a semiconductor wafer, which is placed and held on a sample stage arranged in a processing chamber inside a vacuum container, using a plasma of the processing chamber, and particularly to a plasma processing apparatus or a plasma processing method, that supplies high-frequency power to a sample stage during processing to form a bias potential above an upper surface of the sample, and processes the sample.
2. Description of the Related Art
In general, a technique of etching a film layer, which includes a mask formed in advance on an upper surface of a sample such as a semiconductor wafer, of a processing target having a film structure with plurality of the film layers using a plasma has been performed in a process of manufacturing a semiconductor device as a technique of forming a circuit of the device or a structure of a wiring. Recently, there has been a demand not only for further enhancement of accuracy in such processing using the plasma, but also for reduction of a region, which is a part on an outer peripheral side of the wafer and in which a variation in the processing is out of a tolerance range, so as to reduce the variation with respect to a center side of the processed result according to the processing of even a part on the further outer peripheral side of the wafer, to further increase the number of the devices that can be manufactured for each single wafer, and to enable enhancement of efficiency of the processing along with enhancement of a degree of integration of the semiconductor device.
In general, such a plasma processing apparatus is provided with a vacuum container, a processing chamber, which is arranged in the vacuum container and in which a sample is arranged and a plasma is formed in depressurized interior space, and a vacuum evacuation device which evacuates an inside of the processing chamber to be at pressure with a predetermined degree of vacuum suitable for processing. Further, the plasma processing apparatus is provided with a gas supply device, which is connected to the vacuum container or the vacuum processing chamber and supplies gas for processing the sample in the processing chamber, a sample stage having an upper surface on which the wafer as a material to be processed is placed and held, a plasma generation device which supplies an electric field or a magnetic field for generation of the plasma in the processing chamber into the processing chamber, and the like.
A technique that causes intensity of an electric field, formed above an upper surface of a wafer from a part on a center side to a part on an outer periphery side of the wafer, or distribution thereof to be more uniformly approximated has been considered in order to reduce a region in which a characteristic of processing such as processing speed and a shape after the processing as a result thereof are varied between the center-side part to the part on the outer peripheral side of the wafer, for example, speed (rate) of an etching process is changed. That is, the above-described change in the etching rate in the part on the outer peripheral side of the wafer appears such that the rate increases when the concentration of the electric field is generated in the region on the outer peripheral side of the wafer, and the distribution of a potential or a charged particle of the plasma is lopsided, and thus, it is possible to implement the more uniform processing even to the part on the outer peripheral side of the wafer by suppressing such concentration of the electric field. In order to this, it is effective to adjust the intensity of the electric field, to be formed in a region surrounding the perimeter of the part on the outer peripheral side of the wafer and the distribution thereof, and to set a thickness of a sheath to be formed above the upper surface of the wafer to be more uniformly approximated even to the part on the outer peripheral side in an in-plane direction of the wafer, and particularly, in a radial direction.
A technique, as disclosed in JP-2007-258417-A (Patent Literature 1), of performing control of an electric field between an outer peripheral edge and a region in a vicinity thereof of a wafer during being etched by applying a DC voltage to a focus ring which is a member having conductivity and is arranged to surround the wafer on the outer peripheral side thereof, has been known as a conventional technique of such a plasma processing apparatus. In this conventional technique, a DC voltage value is changed so as to maintain an initial performance depending on the amount of wear of the focus ring caused when the focus ring, which has an upper surface facing a plasma, is abraded due to an interaction with the plasma.
In addition, a configuration, which is provided with a conductor ring arranged on an outer peripheral side on a wafer placement surface of a sample stage to surround a wafer and a dielectric ring cover covering an upper surface of the ring from above the ring, and supplies high-frequency power to the conductor ring while preventing electrical combination with a plasma formed above the ring cover inside a processing chamber, has been disclosed as illustrated in JP-2012-227278-A (Patent Literature 2). Further, this conventional technique also includes a configuration of reducing a variation in height of a bias equipotential surface to be formed above the wafer and the conductor ring, and in angle at which a charged particle of the plasma is incident onto the wafer in a range from a center side to the outer peripheral side of the wafer by setting a height of the conductor ring to be higher than a height of the wafer or an upper surface of the same stage on which the wafer is placed, and accordingly, reducing the variation in the processed shape as a result of the processing.
In addition, JP-2011-9351-A (Patent Literature 3) discloses a technique of adjusting the amount of high-frequency electric power for formation of a bias potential to be applied to a conductive focus ring, which is arranged to surround a wafer on an outer peripheral side of a sample stage, according to a wear amount of the focus ring.